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Application Note 9517
CLK
1.2V REF
3.6V
V RT
CLK
1.3V
V RB
O/UF
26 PIN
CONNECTOR
HI5714
ANALOG
IN1 (DC)
ANALOG
IN2 (AC)
CE
+5VA
V IN
CE
DOUT
8
DAC
+5VD +5VA-5.2VA +12V -12V
FIGURE 3. EVALUATION BOARD BLOCK DIAGRAM
t CPL
t CPH
CLOCK
INPUT
SAMPLE N
SAMPLE N+1
1.4V
SAMPLE N+2
ANALOG
INPUT
t DS
t HD
2.4V
DATA (D0-D7)
OUTPUTS
D N-2
D N-1
t D
D N
D N+1
1.4V
0.4V
FIGURE 4. HI5714 TIMING
Power Supplies and Layout
The HI5714 Evaluation Board is a four layer board with a
layout optimized for the best performance for the ADC.
Figures 11 through 16 include a schematic of the board, a
board layout, and the various board layers. The user should
feel free to copy the layout in their application.
In order optimize the performance of the HI5714 at power
up, it is necessary that AV DD and DV DD be driven from
separate supplies. The supplies to the board should be
driven by clean linear regulated supplies. AGND and DGND
are tied together under
2
the HI5714. Do not tie the supply grounds together back at
the supplies as this will create a ground loop and generate
additional noise.
Decoupling capacitors should be placed as close to the
HI5714 as possible. A 0.1 μ F and a 0.001 μ F leaded capacitor
will provide good decoupling but chip capacitors will provide
better decoupling at higher clock frequencies. Do not forget
a large value cap (1 μ F to 10 μ F) for low frequency
decoupling somewhere on your PC board.
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